1. Field of the Invention
The present invention relates generally to plasma etch methods for forming patterned layers within microelectronics fabrications. More particularly, the present invention relates t0 plasma etch methods for forming patterned oxygen containing plasma etchable layers within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications are formed from microelectronics substrates over which are formed patterned microelectronics conductor layers which are separated by microelectronics dielectric layers.
As microelectronics integration levels have increased and microelectronics device and patterned conductor layer dimensions have decreased, it has become increasingly common within the art of microelectronics fabrication to employ interposed between the patterns of narrow linewidth dimension and/or narrow pitch dimension patterned microelectronics conductor interconnect layers within microelectronics fabrications microelectronics dielectric layers formed of low dielectric constant dielectric materials. Such patterned microelectronics conductor interconnect layers often access within the microelectronics fabrications within which they are formed patterned conductor contact stud layers or patterned conductor interconnect stud layers. For the purposes of the present disclosure, low dielectric constant dielectric materials are intended as dielectric materials having a dielectric constant of less than about 3.0. For comparison purposes, dielectric layers formed employing conventional silicon oxide dielectric materials, silicon nitride dielectric materials or silicon oxynitride dielectric materials typically have dielectric constants in the range of from about 4.0 to about 7.0.
Microelectronics dielectric layers formed of low dielectric constant dielectric materials are desirable interposed between the patterns of narrow linewidth dimension and/or narrow pitch dimension patterned microelectronics conductor layers within microelectronics fabrications since such dielectric layers formed from such low dielectric constant dielectric materials provide dielectric layers which assist in providing microelectronics fabrications exhibiting enhanced microelectronics fabrication speed, attenuated patterned microelectronics conductor layer parasitic capacitance, and attenuated patterned microelectronics conductor layer cross-talk.
Low dielectric constant dielectric materials which may be employed for forming low dielectric constant microelectronics dielectric layers within microelectronics fabrications are typically materials with hydrogen and/or carbon content, such as but not limited to organic polymer spin-on-polymer dielectric materials (such as but not limited to polyimide organic polymer spin-on-polymer dielectric materials, fluorinated polyimide organic polymer spin-on-polymer dielectric materials, poly-arylene-ether organic polymer spin-on-polymer dielectric materials and fluorinated poly-arylene-ether organic polymer spin-on-polymer dielectric materials and fluorinated poly-arylene-ether organic polymer spin-on-polymer dielectric materials), amorphous carbon dielectric materials (such as but not limited to amorphous carbon and fluorinated amorphous carbon), and silsesgiuoxane spin-on-glass (SOG) dielectric materials (such as but not limited to hydrogen silsesquioxane spin-on-glass (SOG) dielectric materials, carbon bonded hydrocarbon silsesquioxane spin-on-glass (SOG) dielectric materials, and carbon bonded fluorocarbon silsesquioxane spin-on-glass (SOG) dielectric materials).
While organic polymer spin-on-polymer dielectric materials, amorphous carbon dielectric materials, and silsesquioxane spin-on-glass (SOG) dielectric materials are thus desirable within the art of microelectronics fabrication for forming low dielectric constant microelectronics dielectric layers interposed between the patterns of patterned conductor interconnect layers which access patterned conductor stud layers within microelectronics fabrications, such microelectronics fabrication structures are often not formed entirely without difficulty. In particular, when such structures are formed employing a damascene method which employs a patterning of a blanket oxygen containing plasma etchable low dielectric constant dielectric layer (such as formed employing an organic polymer spin-on-polymer dielectric material or an amorphous carbon dielectric material) to form a patterned oxygen containing plasma etchable low dielectric constant dielectric layer while employing a hard mask layer and an oxygen containing plasma to form a trench and/or via defined by the patterned oxygen containing plasma etchable low dielectric constant dielectric layer prior to forming a patterned conductor interconnect layer and/or patterned conductor stud layer within the trench and/or via while employing the damascene method, it is often difficult to control the linewidth and sidewall profile of the patterned oxygen containing plasma etchable low dielectric constant dielectric layer, and thus also the linewidth and sidewall profile of the trench and/or via. Trenches and/or vias formed with inadequately controlled linewidth and non-uniform sidewall profile are undesirable within microelectronics fabrications since patterned conductor interconnect layers and/or patterned conductor stud layers formed within those microelectronics fabrications are then also formed with inadequate linewidth control and non-uniform sidewall profiles.
It is thus towards the goal of forming within a microelectronics fabrication a patterned oxygen containing plasma etchable dielectric layer (preferably an oxygen containing plasma etchable low dielectric constant dielectric layer) within which is formed a trench and/or via which may be filled with a patterned conductor interconnect layer and/or a patterned conductor stud layer employing a damascene method, with enhanced linewidth control and uniform sidewall profile, that the present invention is more specifically directed. In a more general sense, the present invention is also directed towards a method for forming a patterned oxygen containing plasma etchable layer, which need not necessarily be a patterned oxygen containing plasma etchable dielectric layer, with enhanced linewidth control and uniform sidewall profile.
Various methods have been disclosed in the art of microelectronics fabrication for forming patterned microelectronics layers within microelectronics fabrications.
For example, Y. J. T. Lii in ULSI Technology, C. Y. Chang and S. M. Sze, eds., Mc-Graw Hill (New York: 1996), pp. 346-55 discloses various plasma process reactor configurations and plasma etchant gas compositions which may be employed when forming patterned layers within microelectronics fabrications while employing plasma etch methods.
In addition, Shan et al., in U.S. Pat. No. 5,514,247, discloses a method for forming within a microelectronics fabrication a via through a dielectric layer to access a conductor metal layer formed beneath the dielectric layer, without forming a sputtered conductor metal residue layer upon a sidewall of the via. The method employs within an etchant gas composition which is employed to etch the via through the dielectric layer a gas which reacts with the conductor metal to form a volatile and readily evacuable material.
Further, Chang et al., in U.S. Pat. No. 5,559,055 discloses a method for forming within a microelectronics fabrication, interposed between a series of patterns of a patterned conductor layer, an interlayer dielectric layer with decreased dielectric constant. The method employs a subtractive etching of an otherwise conventional patterned dielectric layer interposed between the patterns of the patterned conductor layer to form within the microelectronics fabrication a series of air filled voids interposed between patterns of the patterned conductor layer, where the series of air filled voids may subsequently be at least partially filled with a low dielectric constant dielectric material.
Still further, Havemann, in U.S. Pat. No. 5,565,384, discloses a method for forming within a microelectronics fabrication, with attenuated capacitance and attenuated via misalignment induced over-etching, a via accessing a patterned conductor layer within the microelectronics fabrication. The method employs an oxygen containing plasma etchable dielectric material interposed between the patterns of the patterned conductor layer, where the oxygen containing plasma etchable dielectric material serves as an etch stop layer when forming a via through a conventional fluorine containing plasma etchable dielectric layer formed over the oxygen containing plasma etchable dielectric material and the patterned conductor layer.
Finally, various dual damascene methods are disclosed for forming within microelectronics fabrications patterned dielectric layers interposed between the patterns of which may subsequently simultaneously be formed contiguous patterned conductor interconnect layers and patterned conductor stud layers. Specific methods are disclosed by: (1) Huang et al., in U.S. Pat. No. 5,635,423 (dual damascene method employing an etch stop layer interposed between a blanket first dielectric layer through which is formed a via into which is formed a conductor stud layer and a blanket second dielectric layer through which is formed a trench contiguous with the via, within which trench is formed a patterned conductor interconnect layer contiguous with the patterned conductor stud layer); (2) Avanzino et al., in U.S. Pat. No. 5,686,354 (dual damascene method employing a thin via mask formed within a trench formed partially through a dielectric layer, where the via mask is employed to form contiguous with the trench a via completely through the dielectric layer); and (3) Givens, in U.S. Pat. No. 5,726,100 (dual damascene method employing a single mask layer in conjunction with an etch stop layer interposed between a first dielectric layer and a second dielectric layer, where the single mask layer is employed for forming through the first dielectric layer a via contiguous with a trench formed through the second dielectric layer).
Desirable within the art of microelectronics fabrication are methods for forming patterned oxygen containing plasma etchable layers with enhanced linewidth control and uniform sidewall profile. More particularly desirable within the art of microelectronics fabrication are methods for forming patterned oxygen containing plasma etchable dielectric layers, such as oxygen containing plasma etchable low dielectric constant dielectric layers, with enhanced linewidth control and uniform sidewall profile.
It is towards the foregoing objects that the present invention is both generally and more specifically directed.
A first object of the present invention is to provide a method for forming within a microelectronics fabrication a patterned oxygen containing plasma etchable layer.
A second object of the present invention is to provide a method for forming a patterned oxygen containing plasma etchable layer in accord with the first object of the present invention, where the patterned oxygen containing plasma etchable layer is formed with enhanced linewidth control and uniform sidewall profile.
A third object of the present invention is to provide a method in accord with the first object of the present invention or the second object of the present invention, where the microelectronics fabrication is a semiconductor integrated circuit microelectronics fabrication and the patterned oxygen containing plasma etchable layer is a patterned oxygen containing plasma etchable low dielectric constant dielectric layer.
A fourth object of the present invention is to provide a method in accord with the first object of the present invention, the second object of the present invention or the third object of the present invention, which method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for forming a patterned oxygen containing plasma etchable layer within a microelectronics fabrication. To practice the method of the present invention, there is first provided a substrate. There is then formed over the substrate a blanket oxygen containing plasma etchable layer. There is then formed upon the blanket oxygen containing plasma etchable layer a blanket hard mask layer. There is then formed upon the blanket hard mask layer a patterned photoresist layer. There is then etched while employing a first plasma etch method in conjunction with the patterned photoresist layer as a first etch mask layer the blanket hard mask layer to form a patterned hard mask layer. There is then etched while employing a second plasma etch method in conjunction with at least the patterned hard mask layer as a second etch mask layer the blanket oxygen containing plasma etchable layer to form a patterned oxygen containing plasma etchable layer, where the second plasma etch method employs a second etchant gas composition comprising: (1) an oxygen containing etchant gas which upon plasma activation provides an active oxygen containing etching species; and (2) boron trichloride.
There is provided by the present invention a method for forming within a microelectronics fabrication a patterned oxygen containing plasma etchable layer, where the patterned oxygen containing plasma etchable layer is formed with enhanced linewidth control and uniform sidewall profile. The method of the present invention realizes the foregoing objects by employing when forming the patterned oxygen containing plasma etchable layer from a corresponding blanket oxygen containing plasma etchable layer a second plasma etch method employing a second etchant gas composition comprising: (1) an oxygen containing etchant gas which upon plasma activation provides an active oxygen containing etching species; and (2) boron trichloride. While the mechanism through which the method of the present invention realizes the foregoing objects of the present invention is not entirely clear, it is believed that incorporation of boron trichloride in conjunction with the oxygen containing etchant gas provides better linewidth control and a more uniform sidewall profile of the patterned oxygen containing plasma etchable layer, as well as an attenuated surface etching of the patterned hard mask layer employed in forming the patterned oxygen containing plasma etchable layer.
The present invention may be employed where the microelectronics fabrication is a semiconductor integrated circuit microelectronics fabrication and where the patterned oxygen containing plasma etchable layer is a patterned oxygen containing plasma etchable low dielectric constant dielectric layer. The present invention does not discriminate with respect to the nature of a microelectronics fabrication within which is formed a patterned oxygen containing plasma etchable layer in accord with the method of the present invention, nor does the present invention discriminate with respect to the nature of an oxygen containing plasma etchable material from which is formed the oxygen containing plasma etchable layer. Thus, although the method of the present invention provides utility in forming patterned oxygen containing plasma etchable low dielectric constant dielectric layers within semiconductor integrated circuit microelectronics fabrications, the method of the present invention may also be employed in forming patterned oxygen containing plasma etchable layers other than oxygen containing plasma etchable low dielectric constant dielectric layers within microelectronics fabrications including but not limited to semiconductor integrated circuit microelectronics fabrications, solar cell microelectronics fabrications, ceramic substrate microelectronics fabrications and flat panel display microelectronics fabrications.
The present invention is readily commercially implemented. The present invention employs methods and materials which are otherwise generally known in the art of microelectronics fabrication. Since it is a novel ordering and use of methods and materials which provides the method of the present invention, rather than the existence of the methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.